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max14606/max14607 overvoltage protectors with reverse bias blocking typical operating circuit appears at end of data sheet. 19-6147; rev 0; 12/11 ordering inform ation/s elector guide appears at end of data sheet. general description the max14606/max14607 overvoltage protection devic - es feature low 54m i (typ) on-resistance (r on ) internal fets and protect low-voltage systems against voltage faults up to +36v. when the input voltage exceeds the overvoltage threshold, the internal fet is turned off to prevent damage to the protected components. the devices automatically choose the accurate internal trip thresholds. the internal ovlo are preset to typical 5.87v (max14606) or 6.8v (max14607). the max14606/max14607 feature reverse bias blocking capability. unlike other overvoltage protectors, when the max14606 /max14607 are disabled, the voltage applied to out does not feed back into in. these devices also feature thermal shutdown to protect against overcurrent events. the max14606/max14607 are specified over the extend - ed -40 n c to +85 n c temperature range, and are available in 9-bump wlp packages. applications tabletssmart phones portable media players benefits and features s protect high-power portable devices ? wide operating input voltage protection from +2.3v to +36v ? 3a continuous current capability ? integrated 54m i (typ) nmosfet switch s flexible overvoltage protection design ? easy paralleling ? acok indicates input is in range ? preset accurate internal ovlo thresholds 5.87v 3% (max14606) 6.8v 3% (max14607) s additional protection features increase system reliability ? reverse bias blocking capability ? soft-start to minimize inrush current ? internal 15ms startup debounce ? thermal shutdown protection s save space ? 9-bump, 1.3mm x 1.3mm, wlp package visit www.maximintegrated.com/products/patents for product patent marking information. for related parts and recommended products to use with this part, refer to: www.maximintegrated.com/max14606.related . evaluation kit available for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim integrated?s website at www.maximintegrated.com. downloaded from: http:///
max14606/max14607 overvoltage protectors with reverse bias blocking 2 maxim integrated (all voltages referenced to gnd.)in ........................................................................... -0.3v to +40v out ....................................................................... -0.3v to +40v in - out ................................................................... -6v to +40v en , acok ............................................................... -0.3v to +6v ovlo ..................................................................... -0.3v to +10v continuous current into in, out ......................................... q 3a continuous power dissipation (t a = +70 n c) wlp (derate 11.9mw/ n c above +70 n c)......................952mw operating temperature range .......................... -40 n c to +85 n c storage temperature range ............................ -65 n c to +150 n c soldering temperature (reflow) ...................................... +260 n c wlp junction-to-ambient thermal resistance ( b ja )........+84 n c/w absolute maximum ratings note 1: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four-layer board. for detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial . stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress ratings only, and functional opera - tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. package thermal characteristics (note 1) electrical characteristics (v in = +2.3v to +36v, t a = -40 n c to +85 n c, unless otherwise noted. typical values are at v in = +5v, t a = +25 n c.) (note 2) parameter symbol conditions min typ max units input voltage v in v in goes from low to high, acok goes from high to low 2.3 36 v input supply current i in en low, v in = 5v, i out = 0ma 70 120 f a input disable current i in_dis en low, v in = 5v, v ovlo < v ovlo_th 60 120 f a input shutdown current i in_q en high, v in = 5v, v out = 0v 6 12 f a output disable current i out_dis en low, v out = 5v, v in = 5v, v ovlo < v ovlo_th or en low, v out = 5v, v in > v in_ovlo 3 f a output shutdown current i out_sd en high, v out = 5v, v in = 5v 5.5 f a ovp (in to out)on-resistance (in to out) r on v in = 5v, i out = 100ma 54 100 m i internal overvoltage lockout threshold v in_ovlo in rising max14606 5.75 5.87 6.00 v max14607 6.6 6.8 7.0 in falling max14606 5.5 max14607 6.4 out load capacitance c out 1000 f f ovloovlo clamp current v ovlo = 5.5v, v in = 5v 9.7 25 f a ovlo open voltage v ovlo_op v en = 0v 2.95 3.6 v ovlo pullup resistance r ovlo_pu 500 k i ovlo force off voltage v ovlo_th 0.6 1.221 1.4 v downloaded from: http:///
max14606/max14607 overvoltage protectors with reverse bias blocking 3 maxim integrated note 2: all devices are 100% production tested at t a = +25 n c. limits over the operating temperature range are guaranteed by design and not production tested. figure 1. timing diagram electrical characteristics (continued) (v in = +2.3v to +36v, t a = -40 n c to +85 n c, unless otherwise noted. typical values are at v in = +5v, t a = +25 n c.) (note 2) parameter symbol conditions min typ max units digital signals ( en , acok ) en input high voltage v ih 1.4 v en input low voltage v il 0.4 v en input leakage current i en_leak v in_ovlo or 5.5v -1 +1 f a acok output low voltage v ol v io = 3.3v, i sink = 1ma (see the typical operating circuit ) 0.4 v acok leakage current v acok_leak v io = 3.3v, acok deasserted (see the typical operating circuit ) -1 +1 f a timing characteristicsin debounce time t deb 2.3v < v in < v ovlo to charge-pump on, figure 1 10 15 35 ms in/out ovp soft-start time t ss 2.3v < v in < v ovlo to 90% of v out 30 ms ovp turn-on time during soft-start t on v in = 5v, r l = 50 i , c l = 10 f f, v out = 20% of v in to 80% of v in , figure 1 2 ms turn-off time t off v in > v ovlo 2v/ f s to v out = 80% of v in , r l = 50 i , figure 1 1.5 f s en low to high to v out = 80% of v in , r l = 50 i , figure 1 84 thermal protectionthermal shutdown t shdn +150 n c thermal hysteresis t hyst 20 n c t deb t on t off t deb t deb t on t off t deb thermal shutdown ovlo 2.3v in out en acok downloaded from: http:///
max14606/max14607 overvoltage protectors with reverse bias blocking 4 maxim integrated typical operating characteristics (v in = +5v, c in = 1 f f, c out = 1 f f, t a = +25 n c, unless otherwise noted.) supply current vs. supply voltage max14606/7 toc01 in supply voltage (v) in supply current (a) 27 18 9 10 20 30 40 50 60 70 0 03 6 v en = 3v v ovlo = 1v t a = +85c t a = +25c t a = -40c supply current vs. supply voltage max14606/7 toc02 in supply voltage (v) in supply current (a) 27 18 9 50 100 150 200 250 300 350 0 03 6 max14606v en = 0v v ovlo = 3v t a = +85c t a = +25c t a = -40c supply current vs. supply voltage max14606/7 toc03 in supply voltage (v) in supply current (a) 27 18 9 50 100 150 200 250 300 350 0 03 6 t a = +85c t a = +25c t a = -40c v en = 0v v ovlo = 0v output leakage current vs. output voltage max14606/7 toc04 v out (v) output leakage current (a) 5.0 4.5 3.5 4.0 1.0 1.5 2.0 2.5 3.0 0.5 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0 0 5.5 v en = 3v v ovlo = 0v v in = 6v output leakage current vs. output voltage max14606/7 toc05 v out (v) output leakage current (a) 5.0 4.5 0.5 1.0 1.5 2.5 3.0 3.5 2.0 4.0 1 2 3 4 5 6 7 80 0 5.5 v en = 3v v ovlo = 0v v in = 0v normalized r on vs. temperature max14606/7 toc06 temperature (c) normalized r on 60 35 10 -15 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.50.5 -40 85 i out = 100ma normalized ovlo threshold vs. temperature max14606/7 toc07 temperature (c) normalized ovlo threshold 60 35 10 -15 0.96 0.97 0.98 0.99 1.00 1.01 1.02 1.03 1.04 1.050.95 -40 85 ovlo = open debounce time vs. temperature max14606/7 toc08 temperature (c) debounce time (ms) 60 35 10 -15 16 17 18 19 20 21 22 23 24 2515 -40 85 downloaded from: http:///
max14606/max14607 overvoltage protectors with reverse bias blocking 5 maxim integrated typical operating characteristics (continued) (v in = +5v, c in = 1 f f, c out = 1 f f, t a = +25 n c, unless otherwise noted.) power-up response (i out = 0.5a, c out = 100f) max14606/7 toc09 10ms/div 0v0v 0ma v in 5v/divv out 5v/divi out 500ma/div power-up response (i out = 0.5a, c out = 1000f) max14606/7 toc10 10ms/div 0v0v 0ma v in 5v/divv out 5v/divi out 500ma/div overvoltage fault response (max14606, i out = 0.5a, c out = 1f) max14606/7 toc11 10s/div 0v 5v5v 0v 0ma 500ma v in 5v/divv out 5v/divi out 500ma/div downloaded from: http:///
max14606/max14607 overvoltage protectors with reverse bias blocking 6 maxim integrated bump description bump configuration pin name function a1 acok open-drain flag output. acok is driven low after input voltage is stable between minimum v in and v ovlo after debounce. connect a pullup resistor from acok to the logic i/o voltage of the host system. acok is high impedence after thermal shutdown. a2 ovlo overvoltage lockout input. when forced low, it forces the pass element to be switched off. when left unconnected, the part operates normally using its internal ovlo threshold. a3 en active-low enable input. drive en low to turn on the device. drive en high to turn off the device. b1, c1 in overvoltage protection input. bypass in with a 1 f f ceramic capacitor for high q 15kv hbm esd protection. no capacitor is required for q 2kv hbm esd protection. externally connect both in together. b2 i.c. internally connected. i.c. is internally connected to ground. leave i.c. unconnected or connect to gnd. b3, c3 out overvoltage protection output. bypass out with a 1 f f ceramic capacitor. externally connect both out together. c2 gnd ground wlp top view bumps on bottom gnd in out i.c. in out ovlo 2 1 ab c 3 max14606max14607 + acok en downloaded from: http:///
max14606/max14607 overvoltage protectors with reverse bias blocking 7 maxim integrated detailed description the max14606/max14607 overvoltage protection (ovp) devices feature low on-resistance (r on ) internal fets (q1+q2) and protect low-voltage systems against voltage faults up to +36v. if the input voltage exceeds the overvoltage threshold, the output is disconnected from the input to prevent damage to the protected components. the 15ms debounce time prevents false turn-on of the internal fets during startup. soft-start to minimize inrush current, the max14606/max14607 feature a soft-start capability to slowly turn on q1 and q2. soft-start begins when acok is asserted and ends after 15ms (typ). overvoltage lockout (ovlo) the max14606/max14607 use the internal ovlo com - parator with the internally set ovlo value. when in goes above the overvoltage lockout threshold (v in_ovlo ), out is disconnected from in and acok is deasserted. when in drops below v in_ovlo , the debounce time starts counting. after the debounce time, out follows in again and acok is asserted. there are a few options of acok and shutdown condi - tions to choose from with different ovlo and en input combinations ( table 1 ). for applications that need acok present and ovp open, drive en low and use ovlo as a digital input to enable and disable the ovp switch.table 1. logic input table functional diagram en ovlo low high low ovp disabled (reverse blocking present) acok present; i in = 70 f a (typ) ovp shutdown (reverse blocking present) acok not present; i in = 5 f a (typ) high ovp enabled acok present; i in = 70 f a (typ) ovp shutdown (reverse blocking present) acok not present; i in = 5 f a (typ) q1 q2 out gate driver charge pump timing and control logic bg pok v bg r2 in ovlo r ovlo_op v ovlo_op r1 ovlo in en ok max14606/max14607 acok en downloaded from: http:///
max14606/max14607 overvoltage protectors with reverse bias blocking 8 maxim integrated reverse bias blocking when the max14606/max14607 are in overvoltage con - dition, en is high, ovlo is low, or thermal shutdown is on, then the switch between in and out is open and the two back-to-back diodes of the two series switches block reverse bias. therefore, when the voltage is applied at the output, current does not travel back to the input. thermal shutdown protection the max14606/max14607 feature thermal shutdown protection to protect the device from overheating. the device enters thermal shutdown when the junction tem - perature exceeds +150 n c (typ), and the device is back to normal operation again after the temperature drops by approximately 20 n c (typ). in thermal shutdown, the over - voltage protector is disabled and acok is high. applications information in bypass capacitor for most applications, it is recommended to bypass in to gnd with a 1f, 30v ceramic capacitor as close to the device as possible to enable 15kv hbm esd protection on in. in addition, observe good layout practices such as placing the bypass capacitor next to the connector. ic power and ground must also be routed from the connec - tor to the bypass capacitor and then to the max14606/max14607. in this way, the capacitor will absorb the esd energy and thereby protect the device from a high- voltage esd event. out output capacitor the slow turn-on time provides a soft-start function that allows the devices to charge an output capacitor up to 1000 f f without turning off due to an overcurrent condition. esd test conditions esd performance depends on a number of conditions.contact maxim for a reliability report that documents test methodology and results. human body model esd protection figure 2 shows the hbm, and figure 3 shows the cur - rent waveform it generates when discharged into a low-impedance state. this model consists of a 100pf capacitor charged to the esd voltage of interest, which is then discharged into the device through a 1.5k i resistor. figure 2. human body esd test model figure 3. human body current waveform charge-current- limit resistor discharge resistance storagecapacitor c s 100pf r c 1m r d 1.5k high- voltage dc source device under test i p 100% 90% 36.8% t rl time t dl current waveform peak-to-peak ringing(not drawn to scale) i r 10% 0 0 amperes downloaded from: http:///
max14606/max14607 overvoltage protectors with reverse bias blocking 9 maxim integrated typical operating circuit otg en fromsystem charger in pmic krx102 max14607 out inen acok ovlo to system max14607 out inen acok ovlo 1f 1f 1f travel adapter wireless charger v io downloaded from: http:///
max14606/max14607 overvoltage protectors with reverse bias blocking 10 maxim integrated ordering information/selector guide note: all devices are specified over the -40c to +85c operating temperature range. + denotes a lead(pb)-free package/rohs-compliant package. t = tape and reel. package information for the latest package outline information and land patterns (foot - prints), go to www.maximintegrated.com/packages . note that a ?+?, ?#?, or ?-? in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. chip information process: bicmos part ovlo (v) top mark pin-package max14606 ewl+t 5.87 ajr 9 wlp max14607 ewl+t 6.80 ajs 9 wlp package type package code outline no. land pattern no. 9 wlp w91b1+6 21-0430 refer to application note 1891 downloaded from: http:///
max14606/max14607 overvoltage protectors with reverse bias blocking maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim integrated product. no circuit patent licenses are implied. maxim integrated reserves the right to change the circuitry and specifications without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated 160 rio robles, san jose, ca 95134 usa 1-408-601-1000 11 ? 2011 maxim integrated products, inc. maxim integrated and the maxim integrated logo are trademarks of maxim integrated products, inc. revision history revision number revision date description pages changed 0 12/11 initial release ? downloaded from: http:///

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